1. Field of the Invention
The present invention relates to the field of circuit design and, more particularly, to circuit design simulations.
2. Description of the Related Art
The operational speed of modern circuit designs has continually increased. This increase in speed requires highly accurate techniques for ensuring that the circuit design will operate as expected. The circuit design is expressed using some variety of hardware description language and then tested and/or verified using one or more software-based simulation tools. Typically, testing involves subjecting the circuit design to both functional simulation and static timing analysis.
In general, functional simulation refers to the process of ensuring that the logic of the circuit design is correct. Unlike static timing analysis, functional simulation involves the application of user specified input vector(s) to the circuit design. Only the signal paths within the circuit design that are exercised by the applied input vector(s) are evaluated. Accordingly, it may be the case that one or more signal paths in the design are not exercised by a given set of input vectors, and thus, are not evaluated. In fact, the complexity of modern circuit designs makes it difficult to create a set of input vectors that will unquestionably exercise each signal path.
Though functional simulation involves the verification of logic functions, timing analysis also can be performed, albeit on a different level than is performed with respect to static timing analysis. The delay information used during functional simulation typically is specified within a Standard Delay Format (SDF) file as defined by Open Verilog International. The delays specified in an SDF file are fixed in that each represents a timing parameter of the circuit design under a different set of physical circumstances relating to temperature, voltage, or the like. These fixed delays represent delays associated with different components of the circuit design under what can be considered extreme operating conditions, i.e. in terms of a maximum and a minimum. In consequence, the delay information used for functional simulation covers a range of scenarios, but does not reflect variations in conditions that occur during normal operation of the circuit design.
By comparison, static timing analysis involves no input vectors. Instead, static timing analysis can evaluate all possible paths of a circuit design and can indicate a worst case scenario in terms of the delay information that is created on a per signal path basis. The delay information generated during static timing analysis reflects delay variations that may occur during normal operation of a circuit design. Examples of these variations can include, but are not limited to, clock skew, clock uncertainty, or the like. A static timing analysis engine, for example, can determine clock uncertainty for a combination of two or more clock domains. Still, static timing analysis is unable to account for dynamic behavior of the circuit design, i.e. when an input is applied.
In consequence, there can be, and often is, a difference in the results obtained between functional simulation and static timing analysis for the same circuit design. More particularly, the timing information used in functional simulation can be overly optimistic with respect to the signal path delays used. It would be beneficial to provide a technique for improving analysis of circuit designs which overcomes the limitations described above.